I. Field of the Invention:
The invention is directed generally to the field of integrated circuit design, and more particularly to microprocessor controlled apparatus for interconnecting very high speed integrated circuits within multi-chip packages.
II. Discussion of the Prior Art:
Current design practices for designing and interconnecting custom integrated circuit chips typically result in a design with chips interconnected in a semiconductor material, which must communicate with each other, share data buses or other electrical connections directly. Such direct chip-to-chip linkages result in complex routing of signal lines within the chip as well as non-uniform and non-standard input/output requirements. Since known designs are approached on such a non-standard basis, partitioning of designs becomes difficult.
One area where interconnection of integrated circuits is extremely important is the multi-chip package implementation wherein several integrated circuits or "chips" are packaged together in functional blocks. Most known multi-chip package implementations use logic levels for communication between chips. Currently, very few multi-chip packages have been implemented into products because substrate processing technology and packaging have not progressed in density and performance sufficiently to allow a multi-chip package to be considered a functional entity. The multi-chip package presents a significant design problem in cost and complexity, although it is a significant advance in capability.
The invention provides a means for achieving a workable interconnection of integrated circuits, particularly very high speed integrated circuits, utilizing standard interface parts organized about a local data bus. The invention allows for standardization of input/output designs of custom integrated circuits and eliminates the need for designers to consider varying input/output requirements and logic levels in order to achieve interconnection of a plurality of integrated circuit chips in, for example, a multi-chip package. It achieves this by the combination of processor chips and software, standard interfaces and provides the logical interconnection of gates within a chip at the substrate level.
One known approach currently being utilized in multi-chip packaging implementations is shown in FIGS. 1 and 2. This known approach utilizes a functional interface unit 20 such as the Model No. HFIU1616iLBX functional interface unit as available from Honeywell Inc., 1150 East Cheyenne Mountain Blvd., Colorado Springs, Colo. The HFIU1626iLBX is a Functional Interface Unit (FIU) which provides complete protocol and hardware support for interfacing between the HBIU1600ED Bus Interface Unit (BIU), also available from Honeywell Inc., and the iLBX-bus. The FIU is fully compliant with VHSIC Phase 2 in operability standards, PIbus Specification, version 2.1 as required by the Joint Integrated Avionics Working Group (JIAWG) Common Avionics Baseline (CAB) 1 Backplane Standard dated June 1, 1987. The Honeywell FIU handles PI-bus messages and data transfer between the PI-bus, via the FIU and the local bus processor. An internal block diagram of the FIU is shown in FIG. 1.
The basic elements included in the FIU include input/output transceivers 100, clock control 102, test and maintenance controller 104, bus access control 106, register file 108, sync logic 110, input/output transceivers 112, local bus interface 114, memory address generator and cycle controller 116, controller sequence 118 and control registers 120.
As shown in FIG. 2, the PI-bus has a linear, multi-drop, synchronous bus that supports digital message communications between up to 32 modules residing on a single backplane. Messages are transferred datum serial and bit parallel using a datum size of 16 bits per single word or 32 bit per double word.
The prior art implementation includes a local bus 122, interfacing with an FIU 20, which in turn interfaces with a bus interface unit 34 and a test interface unit 124. Communication to the PI-buses 128 and 130, and the test maintenance bus 132 are accomplished through bus transceivers 126.
The PI-bus uses a master-slave communications protocol which allows the bus master to read data from one slave or write data to any number of slaves in a single message sequence. Messages may be routed to particular modules using either logical or physical addressing. A number of independent messages may be transmitted during a bus master's tenure. The message formats provide a 32-bit virtual address range for each module.
The FIU is also compatible with the VHSIC-standard Element Test and Maintenance (ETM) bus interface giving the user chip-level compatibility with other components supporting this standard. The ETM-bus interface monitors on-chip fault detectors and control serial scan, boundary scan, preset, self-test, and other design-for-test functions.
As shown in FIG. 2, the known art utilizes devices such as the FIU 20 to interface between local buses such as the PACE1750A and Motorola 68020 local bus interfaces as well as custom NiLBX buses and other buses such as the PI-bus and Test/Maintenance (TM) buses. As can be seen in FIG. 2, the prior art uses the FIU 20 merely as an interface between buses in connection with a BIU 34. This does not solve the problem of communications between all chips, including custom chips, which may be part of a multichip package. The invention now provides a means for using the FIU and local memory bus, or its equivalent, as a means for interconnecting chips within a multi-chip package so as to cause all major communications among chips within the package to be done on a data passing scheme instead of utilizing customized logic interface circuits for each application wherein one chip must communicate with another.